Target systems comprising two or more processors allow combining flexibility and speed for execution of a set of functions. An example of such a target system is a system having two or more co-processors for executing an application under control of a control processor. Another example is a system having a general-purpose processor and a co-processor, both executing a part of the application. A general-purpose processor is software controlled and can be adapted to many different desired purposes by the use of suitable software, providing a great flexibility. However, for a given function, a software-controlled processor is usually slower than a co-processor dedicated to that function. Examples of co-processors are fixed hardware accelerators, parametrizable hardware accelerators, reconfigurable hardware, application-specific instruction set processors and specialized programmable processors used as accelerators. When using a co-processor, the speed of operation is increased at the expense of flexibility. Furthermore, the use of a co-processor increases the power efficiency of the target system. The co-processor is suitable for the task for which it was designed, but it may not be suitable for a modified version of that task. However, defining a co-processor on a reconfigurable circuit, such as a Field Programmable Gate Array (FPGA), can increase the flexibility of the hardware. Such a logic circuit can be repeatedly configured in different ways.
For target systems comprising both a general-purpose processor and a co-processor, the co-processor is used to execute particular functions, e.g. those requiring speed, and the general-purpose processor can perform the remaining functions under control of the software. The design of such target systems is known as hardware/software co-design. Within the design process, it must be decided, for a target system with a desired functionality, which functions are to be performed by the co-processor and which in software. This is known as hardware/software partitioning. After partitioning the specification of the desired functionality into a part to be implemented in software and a part to be implemented by a co-processor, the actual implementation has to be performed. A compiler converts the part to be implemented in software into machine code to be executed by the general-purpose processor, and for example a hardware synthesis tool configures the hardware or generates a netlist, as defined by its part of the specification.
For other target systems comprising a control processor and two or more co-processors, the co-processors are used to execute the application and the control processor controls the target system, for example handles the operating system and the user interface. The co-processors may be dedicated to efficiently handle a particular set of functions. When designing such a target system a co-design method is applied as well, for determining which functions are executed by a particular co-processor. The specification is partitioned at least into a part to be implemented by a first co-processor and a part to be implemented by a second co-processor.
WO 00/38087 describes a co-design system for making an electronic circuit that includes both a co-processor and software controlled resources. The co-design system receives a behavioral description of the target electronic system and automatically partitions the required functionality between hardware and software. The partitioner generates a control/data-flow graph from an abstract syntax tree. It then operates on the parts of the description that have not already been assigned to resources by the user.
It is a disadvantage of the prior art co-design method that, once the partitioning of the specification has been made, it is not possible to convert the hardware part and/or the software part back to the original source code of the specification. This results in two serious drawbacks. The first is that after partitioning it is practically impossible for the user to make any manual changes to the partitioned specification. This may be very useful in practice to improve the performance of the target system, e.g. by manually transferring additional functionality to a particular co-processor. Secondly, in case of hardware/software co-design, the software compilation and hardware synthesis will have to be performed on the obtained control/data-flow graph representation, meaning that these steps will have to be performed by the same tool used for hardware/software partitioning. In practice, this tool may not generate the most efficient machine code and/or hardware configuration. The use of a compiler specific for the general-purpose processor as well as a design tool and/or compiler specific for the co-processor allows obtaining an optimal performance for the target system. Similar problems are encountered during co-design of a system having a control processor and two or more co-processors for executing an application. In this case the use of dedicated tools for designing the co-processors allows making an optimal design of the target system as well.